1. Field of the Invention
The present invention relates to a level converter used in a multiple supply voltage system required to design a low-power and high-performance semiconductor, and more particularly, to a single supply pass gate level converter (SPLC) for a multiple supply voltage system, which has low power consumption, operates at high speed, and uses only a single supply voltage.
2. Description of the Related Art
A method of reducing a supply voltage in order to realize a low-power semiconductor integrated circuit is an efficient way of reducing power consumption and is disclosed in Reference 1 (R. K. Krishnamurthy, A. Alvandpour, V. De, and S. Borkar, “High-performance and low-power challenges for sub-70 nm microprocessor circuits,” Proc. IEEE Custom Integrated Circuits Conference, May 2002, pp. 125-128). However, this method also reduces a speed of a system so that the overall performance of the system is reduced.
Thus, a multiple supply voltage system has been suggested in Reference 2 (K. Usami, M. Igarashi, F. Minami, T. Ishikawa, M. Kanazawa, M. Ichida, and K. Nogami, “Automated low-power technique exploiting multiple supply voltages applied to a media processor,” IEEE J. Solid-State Circuits, March 1998, vol. 33, no. 3, pp. 463-472) in order to maintain the overall performance and to reduce the power consumption. This multiple supply voltage system is very efficient in reducing leakage power as well as dynamic power.
However, when data of a low supply voltage level drives a gate of a high supply voltage level, a p-channel metal oxide semiconductor (PMOS) transistor is not completely turned off and thus a static current flows therethrough, which is disclosed in Reference 3 (K. Usami and M. Horowitz, “Clustered voltage scaling technique for low-power design,” Proc. International Symposium on Low Power Design, April 1995, pp. 3-8). In order to block a path of such a static current, a level converter that converts data of a low supply voltage level into data of a high supply voltage level should be necessarily used. Thus, an area, power, and delay of the level converter should be minimized in order to minimize an effect of adding the level converter. For this, the level converter is required to include a small number of transistors, have low power consumption, and operate at high speed. Also, the level converter is required to use only a single supply voltage in order to increase convenience in arranging the elements.
However, a pass-transistor half latch disclosed in Reference 4 (F. Ishihara, F. Sheikh, and B. Nikolic, “Level conversion for dual-supply systems,” IEEE Transation VLSI System, February 2004, vol. 12, no. 2, pp. 185-195) and a single supply level converter (SSLC) disclosed in Reference 5 (R. Puri, L. Stok, J. Cohn, D. Kung, D. Pan, D. Sylvester, A. Srivastava, and S. Kulkarni, “Pushing ASIC performance in a power envelope,” Proc. 40th Design Automation Conference, June 2003, pp. 788-793) and Reference 6 (U.S. Pat. No. 7,336,100 B2 (Anthony Correale, Rajiv V. Joshi, David S. Kung, Zhigang Pan, and Ruchir Puri) 2006, Aug. 23.), which are typical level converters, do not satisfy the above conditions.
That is, a level converter is required to include a small number of transistors, have low power consumption, operate at high speed, and use only a single supply voltage in order to minimize an effect of adding the level converter to a multiple supply voltage system and to increase convenience in arranging the elements. However, although a pass-transistor half latch that is a typical level converter has low power consumption and operates at high speed, the pass-transistor half latch uses two supply voltages, thereby leading to difficult arrangements. Although an SSLC that is another typical level converter uses a single supply voltage, the SSLC operates at low speed and has high power consumption. Other typical level converters have similar problems too.
In other words, since a level converter is necessarily used in a multiple supply voltage system, various level converters have been designed and typical level converters such as a cross-coupled PMOS pair level converter, an STR5, and a capacitive based level converter have been suggested in addition to the above-mentioned pass-transistor half latch and the SSLC.
Currently, some semiconductor circuits using the multiple supply voltage system use level converters.